AUTOMATED CONVERSION OF FPGA-TO-ASIC

Mar 16th, 11 / 0 Comments

• From FPGA netlist directly to ASIC gate-level netlist

• Targeting standard fab processes

• Combined with full turnkey ASIC flow

• Tool database includes multiple proven standard-cell
libraries of various standard fab processes

• Tool database libraries are preinstalled and used by the
automated conversion

• For the FPGA area overhead:
Same functionality logic-size is shrunk by 90%

• For the FPGA frequency overhead:
Same frequency is kept but through a cheaper fab process

• Each conversion design is optimized to cost/power and is checked on a variety of  fab processes

• Conversion of any size  and any type of FPGA

FPGA to ASIC Conversions

How does Zero-NRE model for FPGA-to-ASIC conversions work?…

Mar 7th, 11 / 0 Comments

…And how you can afford it.


The “Zero-NRE” model means that the customer doesn’t pay in advance for the one time design cost known also as NRE (Non Recurrent Engineering). The customer places a purchase order for the chips as if they were “off-the-shelf” chips without considering NRE.
Technically, our ability to offer a Zero-NRE model is associated with the functional guarantee we provide.

The functional guarantee is possible because there is no RTL touch and no human errors during the automated conversion phase – a process which is handled by a highly experienced team.

After the customer accepts the quote for the desired quantities, the first order for which the customer delivers a Prototype-Approval-Conditioned-PO (Purchase Order) is placed before we start to work and is actually the conversion project kick-off.

After the stated lead-time, we provide 10 prototypes, in order to let the customer approve the functionality. Once approved, production starts and the first batch of the first order is then shipped according to the agreed terms.

For any additional order beyond the first order, we’ll provide the goods based on the original quote for the “next order”. We provide an end to end solution – we ship finished goods in any format: packaged, bare die, T&R, tubes or any other method requested by the customer.

FPGA to ASIC Conversion

Usually, our model offers a price per final replacement good chip with No NRE charge. We take into account all the NRE expenses including the minimum order lot and calculate them into the chip price accordingly. We find the chip price where a defined quantity of the replacement ASIC chip should be cheaper (or even much cheaper) compared to the FPGA chip price.

The minimum quantity that represents this price is the breakeven point for preferring an ASIC replacement chip over the original FPGA (FPGA to ASIC conversion). If your target is cost, then there is no question about it: you need to pass the breakeven point of minimum quantity.

Since we sell the replacement chips and not the conversion service, the quote is highly associated with the quantity you can commit to produce (you can refer to yearly quantity). As a result, the customer enjoys both the easiness of placing a purchase order for an “off-the-shelf” 2nd source replacement chip and the fast lead-time and seamless process that our unique automated conversion tool can offer.

ASIC Conversions, FPGA to ASIC Conversions, NO NRE

The different Processes of Chip Production

Nov 30th, 10 / 0 Comments

Though FPGA and ASIC designs are quite different, their concept is similar since they both implement logic HW applications. Actually FPGA is some kind of ready-made ASIC with a programmable design, and the only difference between it and a regular full ASIC chip is the fact its logical functions are configurable by the user (FPGA designer), and not pre-determined by the producer of the circuit (ASIC designer).

Of course this is not entirely true, as FPGA’s configurability is somewhat limited and contains a lot of overhead, manifested in power, cost and macimum frequency, but the general idea holds.

Typical ASIC process includes three main stages: definition and exploration, implementation and finally testing before tape-out. The definition stage includes considerations of Marketing, Requirements and Specifications (MRS) in addition to definition of the circuit architecture. After the logic design is simulated and verified, physical implementation stage begins. The final stage is the post layout verification which includes physical and formal parts, plus timing analysis and signal integrity checks.

FGPA of course lacks the manufacturing parts but its programming becomes the main part of the design. Eventually, most of the disadvantages of the FPGA would affect the need of the design to be debugged. Verification would take 50%  and more time of the work. Still the system will be less efficient than ASIC due to its shortcomings, but the save of the pre-design stages is shortening the time until a prototype of the system is created and this is a great advantage.

In conclusion, again we can see that the choice of the design technology is related available to a lot of constraints, such a time to market, budget and several other factors. While an ASIC achieves better results in terms of power, speed and cost, an FPGA benefits from faster time to lab/market.

So the ideal flow would be to combine the two and start off using an FPGA and as soon as the product is ready, convert it to an ASIC and benefit from the reduced power and cost.

ASIC Conversions, FPGA conversions, FPGA to ASIC Conversions

Prototyping with FPGA before converting to ASIC

Sep 12th, 10 / 0 Comments

The time-to-market is one of the most important factors in the success of new products. The road to this success is an hourglass, it’s a matter of time until your competitor will think about the same idea of you may simultaneously release the product to the market, or just before you. A product manager must plan the project as short as possible, since any delay would reduce the profits.

Statisticians claim that being late to market by only 3 months will reduce revenue by 27%. Being late by 12 months will reduce revenues by a staggering 91%!

A guaranteed way to leave a footprint in the market is releasing an early prototype / beta version, which later should be developed. But as hardware design involves a long process of performance optimization and verifications, if a prototype will be designed as ASIC, valuable time would be wasted and if the deadline will be missed, the entire work may go down the drain. Since the ASIC development requires higher costs, even before the development phase, if the project will be lost, it would involve  a  great loss in profitability .

In these cases, a ready-made programmable component, is the best solution. FPGA can  save time and NRE costs, and with enhanced programming of it, a prototype could quickly be developed and ready to hit market. The next step should be converting the FPGA prototype to ASIC in order to improve the product performance, reduce its costs and minimize the disadvantages which FPGA carries.

This one could be done with the conversion services of KaiSemi. In which the flow is handled by KaiSemi and requires very little customer intervention in the process, allowing the costumer to focus on getting the next generation prototype to work and keep one step ahead of the competition.

Actually, nowadays, over a third of all high-end ASIC designers use FPGAs for prototyping design with higher count of logic gates. FPGA vendors actually encourage developers to work at early stages with FPGA components before converting them to ASIC, just as they encourage them to continue working with them even after the prototype development. Encouragement made at the same time the FPGA manufacturers continue to develop better versions of FPGAS while minimizing the disadvantages of the component.

Automated Chip Design Process, End-of-Life Replacement, Multi-Chip Package, NO NRE

FPGA Flexibility Vs KaiSemi Hardening

Aug 15th, 10 / 0 Comments

KAISEMI
Gal Gilat

Dealing with this argument my answer consists of 3 parts:

1. On the marketing aspect:

This exactly the trade-off between FPGA and ASIC, where on one side FPGA is flexible, but, on the other side our ASIC replacement is much cheaper. Note that, usually, companies, that distribute final products that goes to the market in quantities, don’t tend to perform HW change in those, because any HW change in the FPGA involves in huge operation dealing with customers. A better solution is selling another HW version. Therefore, considering final products as a hardened HW, our ASIC replacement is ideal.

2. On the Technology aspect:

On our solution process we add sea of floating spare logic of gates and flops. Once a mistake or a change is required, we offer an  option to fix it by changing only the routing layers by an ECO editor and update the ASIC mask set. The routing layers are about 1/3 of total ASIC mask set, and payment is only for that which is low (for example in a process of 350nm it is about $20K), where the package is not changed and there is no need for having the whole design process again. But if it is a massive design change than it goes to a new design flow.

3. On the Business model aspect:

Since we don’t charge NRE, we provide a chip price for a defined quantity amount, as if you order an off-the-shelf chip with lead-time.

On our offering we provide 2 prices, 1st one is the chip price on the first order quantity and the 2nd one is the chip price on any next order quantity.

On the 1st order quantity – chip price is already 30%-40% cheaper than FPGA, and

on any next order  quantity – chip price is 60%-70% cheaper than FPGA.

Meaning that:

Any order of a defined quantity that you do with us is worthy. You can stop ordering after any obligated order quantity with no penalty.

Of course as long as you perform “next orders” you gain more cost savings.

In case you have a design change you can go to a New Project performing for that again a “First order”.

End-of-Life Replacement, FPGA conversions, FPGA to ASIC Conversions, Uncategorized

Why switch from software DSP to ASIC?

Jul 28th, 10 / 0 Comments

FPGA KAISEMI 1

DSP to ASIC conversion can increase the performance of the chip by several orders of magnitude – between “x3″ to “x100″ or even more, depending on the specific application.

The main reason is that an ASIC chip, as a customizable and functionally flexible design, can consist of hundreds of multipliers that work concurrently thus performing many equivalent SW loops in a single cycle.

The performance is gained because of the following reasons:

  • Loop unrolling technique is paralleling the algorithm, and increasing the number of MAC operations per cycle.
  • Less power is consumed by the system since no memory is needed for the program, plus the clock rate can be a lot slower (a dedicated ASIC can run at 10%-50% the DSP processor clock rate)
  • Since ASIC is all-in-one package, no extra processors and more memory is needed. This assemblage saves power, size and of course work (when utilizing high level synthesis tools).
  • IP security is inherent since there is no external program memory which can be copied or buses that can be monitored using a logic analyzer. Copying an ASIC is practically impossible.
  • Complex digital and analog IP’s can be used in the DSP ASIC, such as Ethernet MAC, high speed USB, PCI, DAC, ADC, etc.
  • The ASIC DSP can incorporate the external glue logic usually required to connect the standard DSP processor to the actual system.
DSP Performance, FPGA conversions, FPGA to ASIC Conversions, Uncategorized

Chip Design: Why switch from FPGA to ASIC

Jul 18th, 10 / 0 Comments

When it comes to implementation of an integrated circuit, there are some factors that should be taken into account before choosing a design method, such as:

  • Time-to-market – how much time do the designers have for development?
  • Complexity of the design – amount of gates and flexible functionality
  • Frequency of the circuit – analog or digital (or mixed), high or low?
  • Ease of implementing changes in the design – is the circuit reprogrammable? updatable? multi-usable? is the design separatable to teams?
  • Anticipated market size – is the circuit intended to be prototypical? for limited or mass production? frequent reconfigurated?
  • And of course, cost considerations – are there Non Recurring Engineering costs? what is the raw price of each unit?

While FPGA strategy’s advantages are related to the re-programmability and the fast production of the design, it lacks most of the other factors. In the following cases FPGA design is not effective:

  • High frequency clock or low power circuit is required – FPGA has some severe limitations in manners of power and timing. The custom nature of ASIC design is supposed to significantly improve the performance of the circuit as it saves power and enables setting higher raw internal clock speeds.
  • Complex design and mixed signal – The complexity of an FPGA is limited since its logic possibilities are pre-defined. When a higher level of logic is needed, FPGA becomes useless, while ASIC is more flexible and enables to customize the capability of the circuit. ASIC has also the ability to integrate pre-designed and verified components such as analog ones which simplify the work with mixed signal circuits.
  • Mass Production and very high volume designs – As a programmable gate-array, FPGA has a readymade netlist with a pre-defined capacity. While sometimes it may be found that a lot of resources are left unused, the size of a unit circuit, and essentially its cost, found to be unnecessarily high. The exact designing of ASIC makes it smaller with maximum use of area, and critically cheaper.
  • Protection and copy-securing of Intellectual Property – as FPGA combines programmability of processors, the “software” of the chip may be leaked. Since FPGA design’s “language” is uniform, material is in risk to reach wrong eyes.

In brief – ASIC is better than FPGA in such cases because:

  • Significantly reduces costs per unit
  • Significantly saving power
  • More secured and protected
  • Smaller form factor
  • Works in higher speeds
ASIC Conversions, Automated Chip Design Process, DSP Performance, End-of-Life Replacement, FPGA conversions, FPGA to ASIC Conversions, Low Power FPGA, Multi-Chip Package, Uncategorized

Inherent FPGA Overhead

Jul 13th, 10 / 0 Comments

(Click to Enlarge)

FPGAs carry much overhead which is cleaned up when converting to an ASIC. The overheads are related to the programmable nature of FPGA which causes massive waste of resources in manners of power, production, configuration, utilization and application.

The spending appears as extra blocks of EPROM/Flash memory, boot loader, IOs and other software-like components which indeed give an advantage to the FPGA as a potentially multi-function device but inherently make it unusable in full efficiency.

The main advantage of the FPGA seems to be its main disadvantage as lot of area, efficiency and design are wasted or lost. ASIC overcomes it as a minimal, effective and custom chip which actually doesn’t require extra blocks and computation elements.

Some of the overheads are:

  • FPGA never reaches the process’s maximum frequency due to routing. Average frequency capability is about 25% to 50% which is equivalent to an ASIC manufactured in an older process generation. A newer one could easily improve the frequency.
  • FPGA requires device programming on/off board final product. In addition, test time per chip is much longer in FPGA and thus typically more expensive.
  • FPGA is bulky wasteful because of unnecessary functionality & logic,  heavy routing and self-software compatibility. Overheads of logic, routing, utilization and configuration make minimal ASIC preferable
    • Each CLB is built from LUTs, FFs and glue logic which are set to one binary function, and actually requires a lot of unused area. The FPGA is bigger and absurdly weaker, ASIC is exactly sized and much more focused.
    • Placement of internal blocks are arranged in vertical tiles which makes the routing longer, much less efficient then ASIC routing. The routing arranged in switch point structure which is built of six pass transistors. Plus, not just the longer wires are lossy, they load lower fan-out as they require extra buffers.
  • FPGA logic utilization never reaches a 100% capacity, but only 75% in average. There are lot of wasted logic and hard blocks such as Memories, DSPs, IOs. Again, ASIC is minimal and exact.
  • The FPGA programming file uploaded on power-up uses an extra large SRAM. It also has an internal boot loader and internal debug infrastructure, which again uses extra memory
  • FGPA packeage comes with additional components such extra EPROM / FLASH memory to store stream bits, and several more units which are not needed for most applications. High pin count BGA package is also supplied for some rare cases. FPGA comes with lot of unnecessary hardware which affects the overall cost, this could be cleaned by an ASIC exact chip.
  • FPGA uses external multi voltage supply: 5v, 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, 1.0v which require extra regulators. FPGA power is 2 to 10 times higher than ASIC.
ASIC Conversions, DSP Performance, FPGA to ASIC Conversions

5 Reasons to Prefer Automated Conversion of FPGA

Jun 30th, 10 / 1 Comment

KAISEMI 2

An automated conversion of FPGA to ASIC at netlist (gate) level is preferable because it overcomes most of the disadvantages of RTL design flow as well as simplifying the ASIC pre-design process.

  • Functionality Guaranteed: The process of converting directly from FPGA netlist does not involve touching or even viewing the original RTL. Since there is no RTL touch, and any involvement of the source code, it leads very little risk because it almost eliminates human errors. The netlist of the proven working FPGA maintains functionality, and the costumer needs not be involved in the process.
  • No NRE Payment: based on minimum quantity ordering, there’s no need to pay the NRE since the process is virtually bulletproof, and the process technology is usually a lot cheaper than that of the original FPGA. The expenses can include only chip products and the NRE is negligible and can be absorbed by the conversion vendor.
  • Fastest cycle-time: The process is limiting the need for customers cycles of RTL flow, synthesis, verifications and back-annotations. Thus, with having well established coherent work flow (a ready made netlist), starting from an higher stage and speeds the reconstruction as ASIC flow. And while the cycle-time is shorten, the quality increased so nothing gets left out. The cycle time of the conversion (including production) is as fast as 6-14 weeks.
  • Any size FPGA is acceptable: The automated process leads to an exceptionally high success rate enabling functionality guarantee for every size and speed rating of FPGA. The process also deals with no limit on netlist size or complexity.
  • No customer intervention: As mentioned, the lack of RTL touch, by starting with functionality maintained  netlist limits the human errors. The customer is required to provide two main receivables: The FPGA netlist (which is ready made), and verification test vectors. From that point on, all is automated, and the whole ASIC process flow until a final working chip is provided.
ASIC Conversions, End-of-Life Replacement, NO NRE

5 stages of typical ASIC flow

Jun 30th, 10 / 0 Comments

FPGA Conversions

The Netlist conversion concept is focused on converting FPGA, directly from the Post-P&R and Netlist level. The customer first delivers his requirements, then the pre-simulation stage will prepare the algorithm to automatically convert the FGPA netlist to ASIC one. Eventually, the algorithm will fabricate all-in-one ASIC-dedicated chip providing all the advantages that were previously explained.

The process generally contains pre-simulation, simulation, synthesis, post-synthesis additional simulation, P&R and final testings. The stages are detailed in the following list:

1. Design-related files delivery from the customer

  • Post compiled Netlist and SDF
  • Functional vectors
  • PIN file
  • Customer checklist
  • Customer Package

2. Pre-Simulation:

  • Completing data inputs from the received files
  • Finding equivalent analog and digital cores
  • Phys/PLL/Analog
  • Core/CPU/DSP/IP
  • Defining required ASIC process and preparing FAB libraries
  • Generating the Memories to ASIC process

3. Simulation:

  • Creating an ASIC Netlist
  • Integration with the equivalent Cores
  • Functional testing measuring fault coverage
  • Floorplanning for power assessments

4. Synthesis & Post-Synthesis simulation:

  • Power analysis and Pads design
  • Preparing to Packaging
  • Testing FABs
  • Running timing iterations (STA, Clock tree etc.)
  • DFT insertions (JTAG, BIST, SCAN etc.)
  • Automatic test pattern generation

5. Layout stage contains:

  • Place & Route
  • SDF timings Gate Level testing
  • running checking tools (DRC/LVS)
  • creating Final Gate files (GDS)
  • Running tests FAB Tape-Out acceptance
ASIC Conversions, Automated Chip Design Process, DSP Performance, End-of-Life Replacement, FPGA to ASIC Conversions, Low Power FPGA, Multi-Chip Package, NO NRE, Uncategorized